1. Field of the Invention
The present invention relates to a nano structure and a method of manufacturing a nano structure.
2. Related Background Art
In recent years, accompanied with the high integration of semiconductor integrated circuits, demand has further increased for forming a fine pattern having a high accuracy.
Heretofore, a pattern forming method using photolithography has been used for the formation of a microstructure.
In the pattern formation by this method, a photosensitizing agent, such as a resist, is applied to a substrate to form a resist film, and after that, this film is exposed and developed on the resist through a photo-mask from a light source such as an ultraviolet ray.
A pattern is transferred on the resist film, and, with this as a mask, a technique for etching the substrate is adopted. After the completion of the processing of the substrate, the resist film is stripped.
In the pattern forming method by this photolithography, a resolving power depends on the wavelength of the light source, and it is particularly difficult to form a pattern having a line width half or less than that of the wavelength of the light source being used.
For example, when a mercury lamp is used as a light source, the wavelength is 365 nm, and when a KrF excimer laser is used, the wavelength is 248 nm.
Consequently, it is difficult to form a pattern having a line width of 500 nm or less by using these light sources. Further, it is difficult to form a pattern having a line width of 100 nm or less. In a case in which such a fine pattern is formed, when it is processed up to the depth of, particularly, 2 μm or more, and, particularly, 10 μm or more, maintaining the processing accuracy becomes more difficult.
Hence, in the formation of the micro pattern having a line width of 500 nm or less (particularly, 100 nm or less), instead of the ultraviolet ray, an electron beam or an ion beam accelerated to 20 to 200 kV is used.
These are referred to as electron beam lithography and ion beam lithography, respectively.
In these electron beam and ion beam lithography techniques, a photo mask is not used, and a pattern can be directly drawn on a resist film by the electron beam or the ion beam.
Further, in recent years, a focus ion beam (FIB) is adopted into a semiconductor manufacturing step.
For example, a pattern forming method of a stepped pattern by the ion beam is proposed in the later part of U.S. Pat. No. 5,236,547, similarly as shown in FIGS. 14, 15A and 15B. FIG. 14 illustrates plots 141 and 142 of ion concentration for the depth of the pattern in the ion beams at low acceleration and high acceleration, respectively. In FIGS. 15A and 15B, reference numeral 1201 denotes a GaAs substrate, reference numeral 1202 denotes a SiNx film, reference numeral 1202a an ion injecting portion, reference numeral 1202b a stepped pattern, reference numeral 1203 a Ga ion, and reference numeral 1204 a CF4 radical.
In this method, at least one of the accelerating voltage of the ion beam, atomic species of the ion, and ion valence is changed, thereby to inject an ion, and after an ion concentration peak area in the depth direction of an etching material is formed, the formation of the stepped pattern is performed by dry etching. Further, international publication WO 03/015145 A1 proposed an implanting process in which, as shown in FIGS. 16A1 to 16D2, a Ga ion is implanted into the GaAs substrate under the presence of a surface oxide film or under the irradiation of oxygen molecules. FIGS. 16A1, 16B1, 16C1 and 16D1 illustrate an aspect after the ion implanting, and FIGS. 16A2, 16B2, 16C2, and 16D2 illustrate an aspect after the etching of an atom layer. The dose amount of the Ga ion in FIGS. 16A, 16B, 16C, and 16D is 6×1013, 6×1014, 6×1015, 6×1017, pcs/cm2, respectively. In FIGS. 16A1 to 16D2, reference numeral 1301 denotes a GaAs layer, reference numeral 1302 a natural oxide film, reference numeral 1303 an oxide film Ga2O3, reference numeral 1304 a Ga ion beam, and reference numeral 1305 the GaAs layer with the Ga ion injected thereto.
Further, Japanese Patent Application Laid-Open No. H04-190984 proposed a method of forming a micro machine, as shown in FIG. 17. In FIG. 17, reference numeral 1401 denotes a Si base substrate, and reference numeral 1402, a focused ion beam. This method adopts a technique in which the Si substrate is directly irradiated by the FIB, such as O, Be, and N, while the accelerated voltage is controlled, thereby to form the micro machine by forming a Si compound area.
Further, Japanese Patent Application Laid-Open No. 2002-368307 discloses a method of manufacturing a magnetoresistance effect film, as illustrated in FIGS. 18A, 18B, and 18C. In these figures, reference numeral 1511 denotes a Si substrate, reference numeral 1512 denotes a laminated film of metallic ferromagnetic layer/insulating layer/metallic ferromagnetic layer, reference numeral 1513 denotes an inorganic resist containing Si, reference numeral 1514 denotes a Ga ion beam, reference numeral 1515 denotes an electron beam, reference numeral 1516 denotes an F based dry etching, reference numeral 1517 denotes a fluorinated gallium compound, and reference numeral 1518 denotes a resist mask.
This is a method of irradiating an electrically neutralized ion beam when the Ga ion beam is injected into a Si containing inorganic resist by irradiating an electron beam in the vicinity of that area.
Further, U.S. Pat. No. 5,236,547 discloses a patterning method, in which Ga ions are implanted into a mask material, such as the SiNx film, as illustrated in FIGS. 19A, 19B, and 19C, thereby etching the mask material.
Further, Japanese Patent Application No. S58-151027 proposed an etching method, as illustrated in FIGS. 20A, 20B, 20C, and 20D. In FIGS. 20A, 20B, 20C, and 20D, reference numeral 1702 denotes an insulating film, reference numeral 1703 denotes a silicon wafer, reference numeral 1704 denotes an ion implanting area, and reference numeral 1705 denotes a non-implanting area. This method is an etching method, in which an ion is implanted with the insulating film on the silicon substrate taken as a mask, and dry etching is performed, thereby forming a step of about 100 nm without a side etching. Further, Japanese Patent Application No. S58-151027 proposes an apparatus at the same time, in which the ion implanting and the dry etching, as illustrated in FIG. 21, are performed in parallel.
In FIG. 21, reference numeral 1711 denotes an ion source, reference numeral 1712 denotes an ion, reference numeral 1713 denotes a magnet to perform a mass separation of the ion, reference numeral 1714 denotes a plasma reaction layer, reference numeral 1715 denotes a work piece object, and reference numeral 1716 denotes a plasma. A method is also proposed, in which the ion implanting and the dry etching are performed in parallel by using such an apparatus.
However, in the pattern forming method by the conventional photolithography, the pattern formation of an extremely fine line width (particularly, 100 nm or less) is difficult. When the line width is processed up to the depth of, particularly, 2 μm or more, and, particularly, 10 μm or more, maintaining the processing accuracy becomes more difficult.
For example, when an attempt is made to fabricate a structure having a depth of 2 μm or more with the resist film as a mask, it is necessary to increase the thickness of the resist film, in order to endure the etching.
Hence, the pattern formation by the line width of 500 nm or less, particularly, 100 nm or less, is difficult.
Further, in the forming method of the stepped pattern according to U.S. Pat. No. 5,236,547, when a mask having concentration peaks at several ion injection depths is formed, it is necessary to change at least one of the accelerated voltage, the atomic species of the ion, and the ion valence and to perform the ion injection. Hence, the change of a condition and the outputting of a condition take time and labor, and, in addition, the etching of the depth of 2 μm or more, and, particularly, 10 μm or more, is difficult. Further, as illustrated in FIG. 14, according to this technique, the implanted ion concentration peak becomes a concentration distribution having the maximal value, not at the uppermost surface of the substrate, but at several injection depths.
Further, in the processing method of implanting the Ga ions according to international publication WO 2003/015145 A1, also, the processing of the GaAs substrate requires heat processing at a high temperature of about 500° C.
Further, in the method of forming the micro machine according to Japanese Patent Application Laid-Open No. H04-190984, since a light element, such as oxygen, is ionized at the pressurized voltage of 40 to 1000 kV or more, a beam spot is about 0.1 μm, and for this reason, the processing of several μm order only can be performed. Further, for the formation of a high aspect step, an application of a higher voltage is required, and therefore, not only is there a limit of the voltage application, but also, as the injection depth becomes deeper, the large lateral spread of the injected ions is produced. Hence, this is not suitable for the high aspect micro pattern formation.
Further, Japanese Patent Application Laid-Open No. 2002-368307, described above, discloses a technique for patterning the Si containing inorganic resist in order to perform the etching of the laminated layer, including a metal magnetic layer. Consequently, after patterning the resist, a process is performed in which the laminated layer, including a lower metal magnetic layer, is further etched, and moreover, the resist is stripped. Further, at the injection time of the Ga ions, since the electron beam is irradiated in the vicinity of that area, the positional accuracy of the Ga ion injection area is affected by the electron beam. This makes it difficult to output the condition of the electron beam irradiation with a good positional accuracy.
Further, U.S. Pat. No. 5,236,547, described above, discloses a technique in which a thin film, such as SiNx and SiO2 on a Si substrate, is used as a mask material, and ions are injected into the mask material. When these processes are used for electronic devices, the Ga ions are likely to affect the device performance, and a high temperature heating process for stripping the mask material containing Ga and taking out the injected Ga is required.
Further, according to Japanese Patent Application No. S58-151027, described above, various ions also can be directly implanted on the entire Si substrate. However, when looking at the ion implanting method of FIG. 21, though this method is configured to deflect ions so as to be irradiated on the substrate, no mention is made of a configuration and an aperture for focusing ions. Consequently, to form the fine pattern, a Si wafer is patterned with a mask, such as an insulating layer, and after that, ion injection is performed, the mask material is removed, and the etching of a non-implanting area is required to be performed. In this method, since ions are configured not to be sufficiently focused as compared with the FIB, the patterning of 100 nm or less is difficult if the mask is not used.
Such a method is difficult to obtain a high etching selection ratio with the mask and the etching material, and therefore, it is difficult to form a structure having a depth of 2 μm or more (particularly, 10 μm or more) with good shape control properties. Particularly, it is difficult to form a high aspect structure, that is, a structure being narrow in width against the depth or the height. Particularly, this is not suitable for the fine pattern, which requires a deep dig (discussed below) with a width of submicrons (particularly, 500 nm or less) and a depth of 2 μm or more.
In view of the above-described problems, an object of the present invention is to provide a nano structure having a pattern of 2 μm or more in depth formed on the surface of the substrate containing Si.
Further, an object of the present invention is to provide a method capable of manufacturing a nano structure having a pattern with a high aspect and a nano order on the substrate containing Si.
The nano structure of the present invention means a structure having a depth of 2 μm or more (particularly, 10 μm or more), such as MEMS (micro electro mechanical system), NEMS (nano electro mechanical system), and an optical device.